Printed circuit boards (PCBs) are used to mechanically support and electrically connect different electronic components using conductive tracks, pads and other features etched from conductive sheets, typically copper. These copper sheets are typically laminated onto a non-conductive substrate. PCBs, also called printed wiring boards (PWBs), can be single sided (with one conductive layer), double sided (two conductive layers), or even multi-layer.
When choosing PCB substrate materials, the mechanical, electrical, chemical, and thermal properties of the material should be taken into consideration. A commonly used resin for commercial applications is FR-4, which is a designation given to a composite material of woven fiberglass cloth with an epoxy resin binder that is flame resistant. Other di-functional and poly-functional epoxies may also be used. The glass transition temperatures of these substrate materials (Tg) typically ranges from 125° C. to 170° C. Polyimide resins with a higher Tg (>200° C.), long-term thermal resistance, and a lower coefficient of thermal expansion (CTE) are used for high-performance multilayer PCBs with a large number of layers.
In the recent past, heat loads on printed circuit assemblies (PCAs) have increased significantly, in some cases rising from approximately 30 W to 130 W. Standard VME (Versa Module Europa) conduction cooling designs (such as VITA 46/48.2) struggle to provide adequate heat dissipation for such a power level, and are strongly dependent on the amount of ECS (Environmental Control System) cooling available. Most of the VME modules consist of a host PCA and one or two mezzanine boards. In the past, most of the heat was concentrated on the host side of the VME module, while nowadays the mezzanine's power dissipation has increased significantly due to their greater functionality. Designers use the mezzanine boards to locate high power central processing units (CPUs) or graphics processing units (GPUs), which can generate high power dissipation of around 50 W. For fan cooling platforms, power limitations are also restricted due to the increase of the components operational temperatures. These factors can cause a reduction in reliability and service life of the boards.
Some cooling solutions for high power PCAs are described in the VITA 48.3 Liquid Cooling standard. However, liquid cooling solutions significantly increase the dimensions of the cooling system since they require additional items (such as: a liquid to air heat exchanger, a pump, a volume compensator, and the like). Other cooling solutions for high power PCBs are described in the VITA 48.5 Air Flow Through Cooling (AFTC) standard. Such an AFTC configuration includes a single airflow channel that extends through an interior cavity of a main chassis unit, as disclosed for example in U.S. Pat. No. 7,995,346 to Biemer et al. As the electronic modules are enclosed within the main chassis unit, the airflow provides cooling of the interior modules without directly exposing the module electronics to direct contact with air, which eliminates the risk of exposure to contaminants in the air.
While such an AFTC configuration suggests a solution to overcome the actual heat power requirements for many PCAs, there remain several limitations which restrict board design, such as the location of high power components, e.g., central processing units (CPUs), graphics processing units (GPUs) and field-programmable gate arrays (FPGAs). Since the VITA 48.5 AFTC is characterized by a single airflow channel with a single inlet and a single outlet, the location of the highest power dissipation is constrained to be located near the inlet area. This restriction can force the designer to add several high power components in the same board, which can result in poor thermal distribution on the board. Furthermore, it can affect the design of the heat exchanger which can cause pressure drop. In order to overcome the heat dissipation, the heat exchanger density has to increase and therefore the pressure drop through the channel increases. The increase in pressure drop induces several limitations on the cooling system, aircraft environmental control system (ECS), or fan cooling.
Conductors on different layers of the PCB are connected with holes in the PCB, which are referred to as “vias”. The most common type of via is a “plated through hole” (PTH), which is formed by drilling a hole through the multilayer PCB and electrochemically plating the hole with a conductive metal, usually copper, providing electrical connections between the layers. Vias may be formed in a variety of configurations. A common configuration is the “stub via”, in which the though portion extends from the top layer to an inner layer, while the stub portion continues from the inner layer junction to the bottom layer. Alternatively, a first stub extends from the top layer to a first inner signal layer, a through portion continues to a second inner layer, and a second stub continues from the second inner layer to the bottom layer. A “through via” is a basic configuration in which there are no stubs but only a through hole extending between the external layers. A “blind via” originates at an external layer and terminates at some inner layer, while a “buried via” connects one or more internal layers only (without connecting to any external layer). A “back-drilled via” is formed using the post-fabrication back-drilling process to remove the stub portions of a PTH via, used in relatively thick PCBs such as thick high-speed backplane designs.
One well known failure mode associated with PCB reliability is the phenomenon of via cracking and PTH fatigue. Via cracking occurs due to the out-of-plane/z-axis mismatch of the coefficient of thermal expansion (CTE) between the copper plating of a PTH via (approximately 17 ppm/° C.) and the surrounding substrate materials (approximately 45-70 ppm/° C.). This material property mismatch leads to differential expansion during temperature variations and the formation of cracks in the via barrel and inner layers as a result of mechanical fatigue. When exposed to thermal cycling, the initiated via cracks may propagate along the copper plated barrel and gradually expand, leading to degradation and eventual PTH failure. In particular, via cracks continually affect electrical discontinuities in the PCB, which can ultimately result in catastrophic failure of the entire PCB-based device. Such a failure is particularly problematic in certain technical fields, such as various military, aerospace, automotive, and medical device applications. PTH fatigue is influenced by various parameters, such as: the maximum and minimum temperatures; the PTH diameter; the copper plating thickness and material properties (e.g., ductility, yield strength); the substrate thickness and material properties (e.g., CTE, elastic modulus); and defects in the copper plating (e.g., voids, folds, etch pits). Reference is made to FIG. 1, which is a cross-sectional schematic illustration of a plated-through hole via with via cracks, as known in the art.
Numerous publications and industry joint efforts cover the key parameters that affect thermal cycle reliability. The strain accumulation depends on strain level induced at each thermal cycle excursion. There are several known approaches for increasing the useful PCB life cycle (i.e., number of thermal cycles before failure). One approach is to decrease the PTH aspect ratio, defined as the ratio between the board thickness and the PTH diameter, for example to less than about 5:1. The smaller the aspect ratio, the more consistent the plating throughout the length of the via. Large aspect ratio vias tend to have greater plating thickness at each end as compared to the center of the barrel, which increases the likelihood of cracked via barrels due to z-axis expansion when soldering. However, decreasing the PTH aspect ratio is extremely difficult (if not impossible) in the current era of High Density Interconnect (HDI) PCB designs. Another approach is to increase the copper (Cu) plating thickness, thereby increasing the space for the via crack to propagate. However, the thickness should be optimized for the process to reduce stress risers due to defects (such as voids in the Cu plating). A standard copper plating thickness is approximately 25 μm, and increasing the thickness beyond around 35 μm is extremely difficult from a manufacturing standpoint.
A further approach would be to improve and test for the adhesion of the Cu foil and the laminate. This option may be theoretically possible, but remains unproven. Yet another approach would be to utilize a Cu material with higher ductility and lower strength, although such a material has not yet been identified commercially. Other options involve decreasing or eliminating thermal shocks during board processing (such as by preheating the board before hot-air leveling, wave soldering, rework, etc), or decreasing the range of thermal cycling, specifically avoiding exposure to temperatures above the glass-transition temperature (Tg) of the resin. These options are not feasible since the board processing requires several necessary thermal processes.
U.S. Pat. No. 8,427,828 to Kehret et al. describes a printed circuit board module that includes a thermal shunt that provides a path between at least some of the electronic components and the front surface of the enclosure. U.S. Pat. No. 8,477,498 to Porecca et al. describes a conduction-cooled apparatus that includes conduction flow paths between a circuit card and the enclosure system. U.S. Pat. No. 8,482,929 to Slaton et al. describes a system for circuit board heat transfer that is configured to transfer heat from the PCB to the chassis through a thermal interface material and a thermal via. U.S. Pat. No. 7,459,200 to McCall et al. describes a circuit board where the fiberglass fibers are disposed in a two-dimensional pattern. U.S. Pat. No. 7,973,244 to Lin et al. describes a printed circuit board that includes a base formed from a plurality of woven fibers, and signal traces laid on the base.
U.S. Pat. No. 6,447,886 to Mohamed et al., entitled “Base material for a printed circuit board formed from a three-dimensional woven fiber structure”, discloses a printed circuit board constructed from a base material formed from a three-dimensional orthogonally woven fabric having a crimp-free fiber architecture in the x-y plane and an integrated multi-layer structure. The base material includes: a first system of straight first fibers extending along a first direction in a first plane, a second system of straight second fibers extending along a second direction in a second plane parallel to the first plane, and a third system of third fibers extending along a third direction through the first and second systems and binding the first and second fibers. The direction of the third fibers may be orthogonal to the respective directions of the first and second fibers. A filler material, such as resin, coats a portion of the first, second and third systems. The printed circuit board further includes one or more conducive layers attached to the surfaces of the base material.
U.S. Pat. No. 5,379,193 to Gall et al., entitled “Parallel processor structure and package”, is directed to a parallel processor package having a plurality of microprocessors and memory modules mounted on printed circuit boards. The printed circuit boards are mounted on a plurality of circuitized flexible substrates or “flex strips”, which connect the separate boards through a relatively rigid central laminate portion. The central laminate portion provides XY plane and Z-axis interconnection and communication (inter-processor, inter-memory, inter-processor/memory and processor to memory bussing). The planar circuitization, as data lines, address lines, and control lines, are on the individual printed circuit boards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (via and through holes) in the central laminate portion.